Semiconductor equipment 200 having a metal oxide semiconductor transistor (i.e., a MOS transistor) according to a prior art is disclosed in Japanese Patent No. 3257057-B2 (Japanese Unexamined Patent Application Publication No. H05-198758). As shown in FIG. 14, the semiconductor equipment 200 includes a semiconductor substrate 3. An insulation layer 4 having a box shape (i.e., a box type insulation layer) is disposed in the substrate 3. The insulation layer 4 has three openings for opening upside of the substrate 3. Each opening is divided by a vertical wall of the insulation layer 4, and accommodates a control unit 5 and two MOS field effect transistors (two MOSFETS) 2A, 2B. The control unit 5 provides a logic circuit or a gate drive circuit.
Each MOSFET 2A, 2B is disposed on the right or left side of the control unit 5, respectively, and is a lateral double-diffused MOSFET (i.e., a L-DMOS). Each L-DMOS 2A, 2B includes a source 21, a drain 22, and a gate 23. The source 21 and the drain 22 are separated in a horizontal direction, and are formed with an impurity diffusion method. Specifically, the source 21 of each L-DMOS 2A, 2B is formed by a double diffusion method, which provides to diffuse from the surface of the substrate 3, and the source 21 is grounded.
A vertical double-diffused MOSFET (i.e., a V-DMOS) 1A, 1B is disposed on both sides of the box type insulation layer 4, i.e., each V-DMOS 1A, 2B is disposed on right or left side of the insulation layer 4, respectively. Each V-DMOS 1A, 1B includes a source 11, a drain 12, and a gate 13. The source 11 is formed by the double diffusion method, which provides to diffuse from the surface of the substrate 3. Both V-DMOS 1A, 1B have the common drain 12, which is disposed on a rear side of the substrate 3 and connects to an electric power source B.
To form the box type insulation layer 4 in the semiconductor equipment 200, it is necessary to form a silicon on insulator structure (i.e., an SOI structure) selectively, as described above. Therefore, the manufacturing cost of the semiconductor equipment 200 becomes higher. Moreover, the drain 12 of the V-DMOS 1A, 1B is common, so that degree of freedom for designing a multi-channel switch formed by a plurality of V-DMOSs becomes lower.
It is considered that an SOI substrate embedding an insulation film therein is used as the substrate 4 so as to lower the manufacturing cost of the semiconductor equipment 200 and to increase the degree of freedom for designing. In this case, an N+ type semiconductor layer as the drain 12 is formed on the insulation layer in the SOI substrate. A resistance of the N+ type semiconductor layer in the V-DMOS becomes a rate-determining factor, so that it is difficult to reduce an ON-state resistance of the V-DMOS.